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data sheet, v1.1, october 2006 spoc - bts 5590gx spi power controller for advanced light control with integrated led mode and watchdog automotive power
spi power controller spoc - bts 5590gx data sheet 2 v1.1, 2006-09-20
spi power controller spoc - bts 5590gx data sheet 3 v1.1, 2006-09-20 table of contents page product summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 pin assignment spoc - bts 5590gx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 block description and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 14 4.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.1 power supply modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.4 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.4 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.5 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.6 loss of v bb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.8 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.1 diagnosis word at spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.2 load current sense diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.3 switch bypass diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5 limp home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5.1 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
spi power controller spoc - bts 5590gx data sheet 4 v1.1, 2006-09-20 table of contents page 4.5.2 trigger state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5.4 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.6.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.6.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.6.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.6.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.5 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6.6 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6 package outlines spoc - bts 5590gx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
data sheet 5 v1.1, 2006-09-20 type package spoc - bts 5590gx p-dso-36-20 spi power controller for advanced light control with integrated led mode and watchdog spoc - bts 5590gx the spoc - bts 5590gx is a five channel high-side smart power switch in p-dso-36-20 package providing embedded protective functions. it is especially designed to control standard exterior lighting in automotive applications. in order to use the same hardware with bulbs and leds, the device can be configured to bulb or led mode. as a result, both load types are handeled optimized in switching and diagnosis accuracy. configuration and status diagnosis is done via spi. additionally, there is a current sense signal available for each channel that is routed via a multiplexer to one diagnosis pin. the spoc - bts 5590gx provides a fail-safe function with integrated watchdog. the watchdog is served via spi by a sophist icated state machine providing secure limp home functionality. product summary operating voltage power switch v bb 4.5 ? 28 v logic supply voltage v dd 3.8 ? 5.5 v over voltage protection v bb(az,min) 41 v maximum stand-by current at 25 c i bb(off) 3 a on-state resistance channel 0, 1 channel 2 channel 3, 4 r ds(on) 25 m ? 40 m ? 100 m ? nominal loads (bulbs) channel 0, 1, 2 channel 3, 4 27 w 10 w spi access frequency f sclk(max) 1mhz p-dso-36-20
spi power controller spoc - bts 5590gx data sheet 6 v1.1, 2006-09-20 basic features ? 8 bit serial peripheral interface (daisy chain capable spi) for control and diagnostics ? cmos compatible parallel input pins for each channel provide straightforward pwm operation ? selectable and- / or-combination for parallel inputs (pwm control) ? very low stand-by current ? optimized electromagnetic compatibility (emc) for bulbs as well as leds ? stable behavior at under voltage ? device ground independent from load ground protective functions ? reverse battery protection with external components ? short circuit protection ? over load protection ? multi step current limitation ? thermal shutdown with latch ? over voltage protection ? loss of ground protection ? electrostatic discharge protection (esd) diagnostic functions ? multiplexed proportional load current sense signals (is) ? enable function for current sense signal configurable via spi ? high accuracy of current sense signal at wide load current range ? current sense ratio ( k ilis ) configurable for leds or bulbs ? very fast diagnosis in led mode (<2% duty cycle at 100 hz) ? feedback on over temperature and over load via spi ? multiplexed switch bypass monitor provides short circuit to v bb detection application specific functions ? integration of adjustable watchdog timer with external capacitor ? sophisticated trigger state machine with two bit increment and lock, served via spi ? fail-safe configuration via input pins ? load type configuration via spi (bulbs or leds) for optimized load control applications ? high-side power switch for 12 v grounded loads in automotive application ? especially designed for standard exterior lighting like tail light, stopping light, reverse light, parking light, license plate lighting, indicators and equivalent leds ? replaces electromechanical relays, fuses and discrete circuits
spi power controller spoc - bts 5590gx data sheet 7 v1.1, 2006-09-20 figure 1 application example abbreviations: sl stopping light (21 w, 27 w) rl reverse light (21 w, 27 w) tl tail light (5 w, 7 w, 10 w) lic license plate lighting (5 w, 10 w) ind indicator / flasher (21 w, 27 w) applicat ionwdrear . emf ind tl rl sl ind tl rl sl spoc lic 100m ? 25m ? 25m ? 40m ? 100m ? 100m ? 25m ? 25m ? 40m ? 100m ? watchdog limp home watchdog limp home fail safe system activation activation spoc - bts 5590gx spoc - bts 5590gx
spi power controller spoc - bts 5590gx overview data sheet 8 v1.1, 2006-09-20 1overview the spoc - bts 5590gx is a five channel high-side power switch in p-dso-36-20 package providing embedded protective functions. there is a watchdog integrated with two bit increment trigger. an 8 bit serial peripheral interface (spi) is used for configuration and diagnosis. the spi can be used in daisy chain configuration. the sophisticated watchdog function provides secure limp home in combination with a limp home out signal. this signal can be individually connected to every input pin. the device provides a current sense signal per channel that is multiplexed to the diagnosis pin is. it can be enabled and disabled via spi commands. an over load and over temperature flag is provided in the spi diagnosis word. a multiplexed switch bypass monitor provides diagnosis at short-circuit to v bb . the power transistors are built by n-cha nnel vertical power mosfets with charge pumps. the device is monolithically integrated in smart sipmos technology. 1.1 block diagram figure 2 block diagram spoc - bts 5590gx 4 3 2 1 vbb channel 0 power supply driver logic gate contr ol & char ge pum p clamp for inductive load load curr ent limitation load cur r ent sense temper atur e sensor esd pr otection in2 in3 in4 in0 in1 out3 out2 out1 out0 out4 current sense multiplexer so sclk is si cs vdd gnd switch bypass monitor esd pr otection lho lhd lhen spi limp home trigger state machine watch dog pwm contr ol led mode control
spi power controller spoc - bts 5590gx overview data sheet 9 v1.1, 2006-09-20 1.2 terms the following figure shows all terms used in this data sheet. figure 3 terms in all tables of electrical characteristics is valid: channel related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds4 ). all spi register bits are marked as follows: addr.parameter (e.g. hwcr.ctl ). in spi register description, the values in bold letters (e.g. 0 ) are default values. ter m s wd. em f i in0 v in0 i in1 v in1 v so i in2 v si i in3 v bb v cs i is i bb in0 in1 in2 in3 is vbb i cs cs sclk v in2 v in3 v in4 v dd i dd i so vdd so i in4 in4 v is i lho lho i lhen i lhd lhen lhd i si si v lhen v lhd v lho out0 i l0 v out1 v out0 v ds1 v ds0 out1 out3 out4 i l1 i l3 i l4 v out3 v out2 v ds3 v ds2 out2 i l2 v out4 v ds4 gnd i gnd i sclk v scl k spoc - bts 5590gx
spi power controller spoc - bts 5590gx pin configuration data sheet 10 v1.1, 2006-09-20 2 pin configuration 2.1 pin assignment spoc - bts 5590gx figure 4 pin configuration p-dso-36-20 2.2 pin definitions and functions pin symbol i/o function power supply pins 1, 18, 19, 36 1) vbb ? positive power supply for high-side power switch and limp home block 3 vdd ? logic supply (5 v) 2 gnd ? ground connection parallel input pins 8 in0 i input signal of channel 0 9 in1 i input signal of channel 1 (top view) out1 out1 out1 vbb 36 35 34 33 32 31 vbb 1 2 3 4 5 6 7 8 30 29 out0 out0 out0 out0 out3 out3 out4 out1 28 27 26 25 24 23 9 10 11 12 13 14 15 16 22 21 out2 out2 out2 out2 out4 vbb 18 19 vbb 20 17 cs sclk si so vdd gnd lhen n.c. is in1 in0 in2 in3 in4 lhd lho
spi power controller spoc - bts 5590gx pin configuration data sheet 11 v1.1, 2006-09-20 10 in2 i input signal of channel 2 11 in3 i input signal of channel 3 12 in4 i input signal of channel 4 power output pins 32, 33, 34, 35 2) out0 o protected high-side power output of channel 0 28, 29, 30, 31 2) out1 o protected high-side power output of channel 1 24, 25, 26, 27 2) out2 o protected high-side power output of channel 2 22, 23 2) out3 o protected high-side power output of channel 3 20, 21 2) out4 o protected high-side power output of channel 4 spi & diagnosis pins 7 cs i chip select of spi interface (low active) 6 sclk i serial clock of spi interface 5 si i serial input of spi interface 4 so o serial output of spi interface 13 is o diagnosis output signal limp home pins 14 lhen i wd and lh enable signal 15 lhd i/o connection for external time base of watchdog 16 lho o limp home output other pins 17 n.c. ? not connected, floating 1) all vbb pins have to be connected. 2) all output pins of each channel have to be connected. pin symbol i/o function
spi power controller spoc - bts 5590gx electrical characteristics data sheet 12 v1.1, 2006-09-20 3 electrical characteristics 3.1 maximum ratings stresses above the ones listed here may affect device reliability or may cause permanent damage to the device. unless otherwise specified: t j = 25 c pos. parameter symbol limit values unit conditions min. max. supply voltage 3.1.1 power supply voltage v bb -0.3 28 v 3.1.2 logic supply voltage v dd -0.3 5.5 v 3.1.3 reverse polarity voltage according figure 26 - v bat(rev) 16 v t jstart = 25 c t 2min 1) 3.1.4 supply voltage for full short circuit protection (single pulse) ( t j(0) = -40 c ? 150 c) v bb(sc) 020v l sc = 5 h, r sc = 0.1 ? 3.1.5 voltage at power transistor v ds 54 v 3.1.6 supply voltage for load dump protection v bb(ld) 41 v r i = 2 ? 2) 3.1.7 current through ground pin i gnd -100 25 ma t 2min 3.1.8 current through vdd pin i dd -25 12 ma t 2min power stages 3.1.9 load current i l -i l(lim) i l(lim) a 3) diagnosis pin 3.1.10 current through sense pin is i is -10 10 ma t 2min input pins 3.1.11 voltage at input pins v in -0.3 8.0 v 3.1.12 current through input pins i in 0 -2.0 0.75 2.0 ma t 2min spi pins 3.1.13 voltage at chip select pin v cs -0.3 5.7 v 3.1.14 current through chip select pin i cs -2.0 2.0 ma t 2min 3.1.15 voltage at serial input pin v si -0.3 5.7 v
spi power controller spoc - bts 5590gx electrical characteristics data sheet 13 v1.1, 2006-09-20 3.1.16 current through serial input pin i si -2.0 2.0 ma t 2min 3.1.17 voltage at serial clock pin v sclk -0.3 5.7 v 3.1.18 current through serial clock pin i sclk -2.0 2.0 ma t 2min 3.1.19 current through serial output pin so i so -2.0 2.0 ma t 2min limp home pins 3.1.20 voltage at limp home enable pin v lhen -0.3 8.0 v 3.1.21 current through limp home enable pin i lhen 0 -2.0 0.75 2.0 ma t 2min 3.1.22 current through limp home output pin i lho -2.0 2.0 ma t 2min 3.1.23 voltage at limp home delay pin v lhd -0.3 5.7 v 3.1.24 current through limp home delay pin i lhd -1.0 1.0 ma t 2min temperatures 3.1.25 junction temperature t j -40 150 c 3.1.26 dynamic temperature increase while switching ? t j 60 c 3.1.27 storage temperature t stg -55 150 c esd susceptibility 3.1.28 esd susceptibility hbm outpins other pins v esd -4 -2 4 2 kv according to eia/jesd 22-a 114 1) device mounted on pcb (40 mm 40 mm 1.5 mm epoxy, fr4) with maximum copper heatsinking area (two layer, 70 m thick with vias) for v bb connection. pcb is vertical without blown air. 2) r i is the internal resistance of the load dump pulse generator. 3) current limitation is a protection feature. operation in current limitation is considered as ?outside? normal operating range. protection features are not designed for continuous repetitive operation. unless otherwise specified: t j = 25 c pos. parameter symbol limit values unit conditions min. max.
spi power controller spoc - bts 5590gx power supply data sheet 14 v1.1, 2006-09-20 4 block description and electrical characteristics 4.1 power supply the spoc - bts 5590gx is supplied by two supply voltages v bb and v dd . the v bb supply line is used by the power switches and by an internal power supply for the limp home function. the limp home power supply is enabled by pin lhen. as a result, the stand-by current is minimized only when limp home function is disabled. the v dd supply line is used by the spi related circuitry and for driving the so line. a capacitor between pins vdd and gnd is recommended. there is a power-on reset function implemented for the v dd logic supply voltage. after start-up of the logic power supply, all spi registers are reset to their default values. the spi interface including daisy chain function is active as soon as v dd is provided in the specified range independent of v bb . 4.1.1 power supply modes the following table shows all possible power supply modes for v bb , v dd and the internal power supply that is enabled by pin lhen. to achieve stand-by mode, the limp home block must be disabled (lhen = 0 v), all channels must be switched off and the thermal latches have to be cleared. as a result the stand-by current i bb(off) is valid as listed. in case of active v dd supply, the idle mode power supply modes vbb 0 v 0 v 0 v 0 v 13.5 v 13.5 v 13.5 v 13.5 v vdd 0v0v5v5v0v0v5v5v lhen 0v 5v 0v 5v 0v 5v 0v 5v profet operating ? ? ? ? ???? watchdog active ? ? ? ? ? ? 1) 1) an active and unserved watchdog will cause limp home mode after overrun. ? ? 1) spi (logic) reset reset ?? reset reset ?? 2) 2) spi reset in limp home mode. stand-by current ? ??? idle current ? ? ? 3) 3) when all channels are in off-state and all spi registers are at default values. ? diagnosis ? ? ?? 4) 4) current sense diagnosis not available in limp home mode.
spi power controller spoc - bts 5590gx power supply data sheet 15 v1.1, 2006-09-20 parameters are valid only, when additionally all spi registers are at default values (see section 4.6.6 ) e.g. after a reset command. 4.1.2 reset there are several reset trigger implemented in the device. they reset the spi registers to their default values. the power stages as well as the analog watchdog block are not affected by the reset signals. the first spi transmission after any kind of reset contains at pin so the read information from register out , and the transmission error bit ter is set. power-on reset. the power-on reset is released, when v dd voltage level is higher than v dd(po) . the spi interface can be accessed after wake up time t wu(po) . reset command. there is a reset command available to reset all register bits of the register bank and the diagnosis registers. as soon as hwcr.rst = 1, a reset is triggered equivalent to power-on reset. the spi interface can be accessed after transfer delay time t sc(td) . limp home mode. in limp home mode, the spi write-registers are reset. the spi interface is operating normally, so the limp home register bits lho and lhen as well as the error flags can be read.
spi power controller spoc - bts 5590gx power supply data sheet 16 v1.1, 2006-09-20 4.1.3 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. 4.1.1 operating voltage power switch v bb 4.5 28 v 4.1.2 operating voltage watchdog v bb(wd) 928 1) v 4.1.3 stand-by current for whole device with loads i bb(off) 1.2 3 3 50 a v dd = 0 v v lhen = 0 v v in = 0 v t j = 25 c t j 85 c 1) t j = 150 c idle current for whole device with loads i bb(idle) 3 3 50 a v dd = 5 v v lhen = 0 v v in = 0 v t j = 25 c t j 85 c 1) t j = 150 c 4.1.4 logic supply voltage v dd 3.8 5.5 v 4.1.5 logic supply current i dd 45 150 a v cs = 0 v f sclk = 0 hz 4.1.6 logic idle current i dd(idle) 15 35 a v cs = v dd f sclk = 0 hz 4.1.7 operating current for whole device i gnd 10 20 ma f sclk = 0 hz
spi power controller spoc - bts 5590gx power supply data sheet 17 v1.1, 2006-09-20 note: characteristics show the deviation of parameter at the given supply voltage and junction temperature. typical values show the typical parameters expected from manufacturing at v bb = 13.5 v, v dd = 4.3 v and t j = 25 c reset 4.1.8 power-on reset threshold voltage v dd(po) 3.8 v 4.1.9 power-on wake up time t wu(po) 500 s 1) not subject to production test, specified by design. unless otherwise specified: v bb = 9 v to 16 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx power supply data sheet 18 v1.1, 2006-09-20 4.1.4 command description hwcr hardware configuration register w/r 43210 read lho wdl sbm pwm ctl write rst wdl 0 pwm ctl field bits type description rst 4 r reset command 0 normal operation 1 device in reset due to limp home mode w reset command 0 normal operation 1 execute reset command
spi power controller spoc - bts 5590gx power stages data sheet 19 v1.1, 2006-09-20 4.2 power stages the high-side power stages are built by n-channel vertical power mosfets (dmos) with charge pumps. there are five channels implemented in the device. each channel can be switched on via an input pin or via spi register out . channels 0, 1 and 2 provide a load type configuration for bulbs or leds in register wdlr . the load type configuration is allowed to be changed in off-state only. 4.2.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage v bb as well as on the junction temperature t j . figure 5 shows those dependencies. the behavior in reverse polarity mode is described in section 4.3.3 . figure 5 typical on-state resistance 4.2.2 input circuit there are two ways of using the input pins in combination with the out register by programming the hwcr.pwm parameter. ? hwcr.pwm = 0: a channel is switched on either by the according out register bit or the input pin ? hwcr.pwm = 1: a channel is switched on by the according out register bit only, when the input pin is high. in this configuration, a pwm signal can be given to the input pin and the channel is activated by the spi register out figure 6 shows the complete input switch matrix. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 150 r ds(on) /m ? t / c channel 0, 1 (bulb) channel 0, 1 (led) channel 2 (bulb) channel 2 (led) channel 3, 4 50 100 150 200 250 0 5 10 15 20 25 r ds(on) /m ? v bb /v channel 0, 1 (bulb) channel 0, 1 (led) channel 2 (bulb) channel 2 (led) channel 3, 4 v bb = 13.5 v t j = 25 c
spi power controller spoc - bts 5590gx power stages data sheet 20 v1.1, 2006-09-20 figure 6 input switch matrix the current sink to ground at the input pins ensures that the input signal is low in case of an open input pin. the zener diode protects the input circuit against esd pulses. 4.2.3 power stage output the power stages are built to be used in high side configuration ( figure 7 ). figure 7 power stage output the power dmos switches with a dedicated slope, which is optimized in terms of emc emission. i nput mat rix. emf in0 in1 in2 in3 in4 gate driver 2 gate driver 1 gate driver 0 gate driver 4 gate driver 3 & or out2 out1 out0 out4 out3 & or & or & or & or pwm i in0 i in1 i in2 i in3 i in4 out put . emf out gnd v out vbb v on v bb
spi power controller spoc - bts 5590gx power stages data sheet 21 v1.1, 2006-09-20 figure 8 switching a load (resistive) when switching off inductive loads with high-side switches, the voltage v out drops below ground potential, because the inductance intends to continue driving the current. to prevent destruction of the device, there is a voltage clamp mechanism implemented that limits that negative output voltage to a certain level ( v on(cl) ( 4.2.3 )). see figure 7 for details. the maximum allowed load inductance is limited. in v out t switchon.emf t on t off t 90% 10% 70% d v / d t on 30% 70% d v / d t off 30%
spi power controller spoc - bts 5590gx power stages data sheet 22 v1.1, 2006-09-20 4.2.4 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. output characteristics 4.2.1 on-state resistance r ds(on) m ? channel 0, 1 22.8 74 50 150 wdlr.ledn = 0 i l = 2.6 a wdlr.ledn = 1 i l = 700 ma channel 2 31.5 91 80 240 wdlr.ledn = 0 i l = 2.6 a wdlr.ledn = 1 i l = 700 ma channel 3, 4 81 200 i l = 1 a 4.2.2 output voltage drop limitation at small load currents v ds(nl) mv channel 0, 1, 2 35 i l = 35 ma channel 3, 4 35 i l = 35 ma 4.2.3 output clamp v on(cl) 41 47 54 v i l = 20 ma 4.2.4 output leakage current per channel i l(off) a v in = 0 v out.outn = 0 channel 0, 1 0.1 10 40 v lhen = 0 v v lhen = 5 v channel 2 0.1 10 40 v lhen = 0 v v lhen = 5 v channel 3, 4 0.1 8 40 v lhen = 0 v v lhen = 5 v 4.2.5 inverse current capability per channel -i l(ic) a no influence on functionality of unaffected channels 1) channel 0, 1, 2 2.5 channel 3, 4 1.0
spi power controller spoc - bts 5590gx power stages data sheet 23 v1.1, 2006-09-20 thermal resistance 4.2.6 junction to case r thjc 20 k/w 1) 4.2.7 junction to ambient, all channels active r thja 40 k/w 1) 2) input characteristics 4.2.8 l-input level v in(l) -0.3 1.0 v 4.2.9 h-input level v in(h) 2.6 5.5 v 4.2.10 l-input current i in(l) 32575 a v in = 0.4 v 4.2.11 h-input current i in(h) 10 40 75 a v in = 5 v timings 4.2.12 turn-on time to 90% v bb t on s v bb = 13.5 v channel 0, 1, 2 250 100 wdlr.ledn = 0 r l = 6.8 ? wdlr.ledn = 1 r l = 33 ? channel 3, 4 250 r l = 18 ? 4.2.13 turn-off time to 10% v bb t off s v bb = 13.5 v channel 0, 1, 2 290 120 wdlr.ledn = 0 r l = 6.8 ? wdlr.ledn = 1 r l = 33 ? channel 3, 4 290 r l = 18 ? 4.2.14 turn-on slew rate 30% to 70% v bb d v / d t on v/ s v bb = 13.5 v channel 0, 1, 2 0.1 0.1 0.5 1.5 wdlr.ledn = 0 r l = 6.8 ? wdlr.ledn = 1 r l = 33 ? channel 3, 4 0.1 0.5 r l = 18 ? unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx power stages data sheet 24 v1.1, 2006-09-20 4.2.15 turn-off slew rate 70% to 30% v bb -d v / d t off v/ s v bb = 13.5 v channel 0, 1, 2 0.1 0.1 0.5 1.5 wdlr.ledn = 0 r l = 6.8 ? wdlr.ledn = 1 r l = 33 ? channel 3, 4 0.1 0.5 r l = 18 ? 1) not subject to production test, specified by design. 2) device mounted on pcb (40 mm 40 mm 1.5 mm epoxy, fr4) with maximum copper heatsinking area (two layer, 70 m thick with vias) for v bb connection. pcb is vertical without blown air. unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx power stages data sheet 25 v1.1, 2006-09-20 4.2.5 command description out output configuration registers 43210 out4 out3 out2 out1 out0 field bits type description outn n = 4 to 0 nrw set output mode for channel n 0 channel n is switched off 1 channel n is switched on wdlr watchdog and led mode configuration register w/r 43210 read wdc led2 led1 led0 write wdtr led2 led1 led0 field bits type description ledn n = 2 to 0 nrw set led mode for channel n 0 channel n is in bulb mode 1 channel n is in led mode
spi power controller spoc - bts 5590gx power stages data sheet 26 v1.1, 2006-09-20 hwcr hardware configuration register w/r 43210 read lho wdl sbm pwm ctl write rst wdl 0pwm ctl field bits type description pwm 1 rw pwm configuration 0 input signal or-combined with according out register bit 1 input signal and-combined with according out register bit
spi power controller spoc - bts 5590gx protection functions data sheet 27 v1.1, 2006-09-20 4.3 protection functions the device provides embedded protective functions, which are designed to prevent ic destruction under fault conditions described in this data sheet. fault conditions are considered as ?outside? normal operating range. protective functions are neither designed for continuous nor for repetitive operation. 4.3.1 over load protection the load current i l is limited by the device itself in case of over load or short circuit to ground. there are multiple steps of current limitation which are selected automatically depending on the voltage v ds across the power dmos. please note that the voltage at the out pin is v bb - v ds . please refer to following figures for details. figure 9 current limitation channels 0, 1 (minimum values) figure 10 current limitation channels 2 (minimum values) currentlimitation01l .emf 5101520 v ds 25 i l 5 10 15 20 25 wdlr.led = 0 wdlr.led = 1 currentlimitation2l .emf 5101520 v ds 25 i l 5 10 15 20 25 wdlr.led = 0 wdlr.led = 1
spi power controller spoc - bts 5590gx protection functions data sheet 28 v1.1, 2006-09-20 figure 11 current limitation channels 3, 4 (minimum values) current limitation to the value i l(lim) is realized by increasing the resistance of the output channel, which leads to rapid temperature rise inside. 4.3.2 over temperature protection a temperature sensor for each channel causes an overheated channel to switch off latched to prevent destruction. all over temperature latches are cleared by spi command hwcr.ctl = 1. figure 12 shut down by over temperature 4.3.3 reverse polarity protection in reverse polarity mode, power dissipation is caused by the intrinsic body diode of each dmos channel as well as each esd diode of the logic pins. the reverse current through the channels has to be limited by the connected loads. the current trough the ground pin, sense pin is, the logic power supply pin vdd, the spi pins and the watchdog pins has to be limited as well (please refer to the maximum ratings listed on page 12 ). note: no other protection mechanism like te mperature protection or current limitation is active during reverse polarity. currentlimitation34 .emf i l 5101520 v ds 25 2 4 6 8 10 12 in i l i is t i l(lim) t t err t overload.emf ctl = 1
spi power controller spoc - bts 5590gx protection functions data sheet 29 v1.1, 2006-09-20 4.3.4 over voltage protection in addition to the output clamp for inductive loads as described in section 4.2.3 , there is a clamp mechanism available for over voltage protection. the current through the ground connection has to be limited during over voltage. please note that in case of over voltage the pin gnd might have a high voltage offset to the module ground. 4.3.5 loss of ground in case of complete loss of the device ground connections, but connected load ground, the spoc - bts 5590gx securely changes to or stays in off-state. 4.3.6 loss of v bb in case of loss of v bb connection in on-state, all inductance of the loads has to be demagnetized through the ground connection or through an additional path from vbb to ground. when a diode is used in the ground path for reverse polarity reason, the ground connection is not available for demagnetization. then for example, a resistor can be placed in parallel to the diode or a suppressor diode can be used between vbb and gnd.
spi power controller spoc - bts 5590gx protection functions data sheet 30 v1.1, 2006-09-20 4.3.7 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. over load protection 4.3.1 load current limitation i l(lim) a v ds = 7 v channel 0, 1 24 7 48 1) 18 wdlr.ledn = 0 wdlr.ledn = 1 channel 2 24 7 48 1) 18 wdlr.ledn = 0 wdlr.ledn = 1 channel 3, 4 12 27 4.3.2 initial short circuit shut down time t off(sc) s t jstart = 25 c 1) channel 0, 1 550 500 wdlr.ledn = 0 wdlr.ledn = 1 channel 2 400 350 wdlr.ledn = 0 wdlr.ledn = 1 channel 3, 4 400 over temperature protection 4.3.3 thermal shut down temperature t j(sc) 150 170 1) c 4.3.4 thermal hysteresis ? t j 7k 1) reverse battery 4.3.5 drain-source diode voltage ( v out > v bb ) -v ds(rev) mv t j = 150 c channel 0, 1 600 i l = -2.5 a channel 2 620 i l = -2.5 a channel 3, 4 600 i l = -1 a over voltage 4.3.6 overvoltage protection v bb(az) 41 47 54 v i bb = 4 ma
spi power controller spoc - bts 5590gx protection functions data sheet 31 v1.1, 2006-09-20 loss of gnd protection 4.3.7 output current while gnd disconnected i l(gnd) 1ma 1) 1) not subject to production test, specified by design. unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx protection functions data sheet 32 v1.1, 2006-09-20 4.3.8 command description hwcr hardware configuration register w/r 43210 read lho wdl sbm pwm ctl write rst wdl 0 pwm ctl field bits type description ctl 0 rw clear thermal latch 0 thermal latches are untouched 1 command: clear all thermal latches
spi power controller spoc - bts 5590gx diagnosis data sheet 33 v1.1, 2006-09-20 4.4 diagnosis for diagnosis purpose, the spoc - bts 5590gx provides a current sense signal and the diagnosis word at spi. there is a current sense multiplexer implemented that is controlled via spi. the sense signal can also be disabled by spi command. a switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. please refer to figure 13 for details. figure 13 block diagram: diagnosis channel 0 load current sense diagnosisl.emf r is led0 i is 0 ( l e d ) i is 0 1 0 cur rent sense multiplexer is t gate control load curr ent limitation latch tem perature sensor err0 or latch dcr.mux sbm hwcr. out4 out3 out2 out1 out0 vbb v bb v ds(sb) wdlr.
spi power controller spoc - bts 5590gx diagnosis data sheet 34 v1.1, 2006-09-20 for diagnosis feedback at different operation modes, please see following table. 4.4.1 diagnosis word at spi the standard diagnosis at the spi interface provides information about each channel. the error flags, an or combination of the over temperature flags and the over load monitoring signals are provided in the spi standard diagnosis bits errn . the over load monitoring signals are latched in the error flags and cleared each time the standard diagnosis is transmitted via spi. in detail, they are cleared between the second and third raising edge of the sclk signal. the over temperature flags, which cause an overheated channel to stay switched off, are latched directly at the gate control block. the latches are cleared by spi command hwcr.ctl . please note: the over temperature information is latched twice. when transmitting a clear thermal latch command ( hwcr.clt ), the error flag is cleared during command transmission of the next spi frame and ready for latching after the third raising edge of the sclk signal. as a result, the first standard diagnosis information after a ctl command will indicate a failure mode at the previously affected channels although the table 1 operation modes 1) 1) l = low level, h = high level, z = high impedance, potential depends on leakage currents and external circuit x = undefined operation mode input level out.outn output level v out current sense i is error flag errn 2) 2) the error flags are latched until they are transmitted in the standard diagnosis word via spi hwcr. sbm normal operation (off) l / 0 (off-state) gnd z 0 1 short circuit to gnd gnd z 0 1 over temperature z z 0 x short circuit to v bb v bb z00 open load z z 0 x normal operation (on) h / 1 (on-state) ~ v bb i l / k ilis 00 current limitation < v bb z1x short circuit to gnd ~gnd z 1 1 over temperature z z 1 3) 3) the over temperature flag is set latched and can be cleared by spi command hwcr.ctl x short circuit to v bb v bb < i l / k ilis 00 open load v bb z00
spi power controller spoc - bts 5590gx diagnosis data sheet 35 v1.1, 2006-09-20 thermal latches have been cleared already. in case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. 4.4.2 load current sense diagnosis there is a current sense signal available at pin is which provides a current proportional to the load current of one selected channel. the selection is done by a multiplexer which is configured via spi. current sense signal the current sense signal (ratio k ilis = i l / i s ) is provided as long as no failure mode occurs. the ratio k ilis can be adjusted to the load type (led or bulb) via spi register wdlr for channels 0 to 2. usually a resistor r is is connected to the current sense pin. it is recommended to use resistors 2.5 k ?< r is <7k ? . a typical value is 3.3 k ? . figure 14 current sense ratio k ilis channel 0,1 1) 1) the curves show the behavior based on characterization data. the marked points are guaranteed in this data sheet in section 4.4.4 (position 4.4.1 ). 1000 2000 3000 4000 5000 6000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 k ilis i l0,1 /a dummy bulb: t j = 150 c dummy bulb: t j = -40 c dummy led: t j = 150 c dummy led: t j = -40 c
spi power controller spoc - bts 5590gx diagnosis data sheet 36 v1.1, 2006-09-20 figure 15 current sense ratio k ilis channel 2 1) figure 16 current sense ratio k ilis channel 3, 4 1) 1) the curves show the behavior based on characterization data. the marked points are guaranteed in this data sheet in section 4.4.4 (position 4.4.1 ). 1000 2000 3000 4000 5000 6000 0 0.5 1 1.5 2 2.5 3 3.5 4 k ilis i l2 /a dummy bulb: t j = 150 c dummy bulb: t j = -40 c dummy led: t j = 150 c dummy led: t j = -40 c 500 1000 1500 2000 2500 3000 0 0.5 1 1.5 2 k ilis i l3,4 /a dummy t j = 150 c dummy t j = -40 c
spi power controller spoc - bts 5590gx diagnosis data sheet 37 v1.1, 2006-09-20 in case of over current as well as over temperature, the current sense signal of the affected channel is switched off. to distinguish between over temperature and over load, the spi diagnosis word can be used. whereas the over load flag is cleared every time the diagnosis is transmitted, the over temperature flag is cleared by a dedicated spi command ( hwcr.ctl ). details about timings between the current sense signal i is and the output voltage v out and the load current i l can be found in figure 17 . figure 17 timing of current sense signal current sense multiplexer there is a current sense multiplexer implemented in the spoc - bts 5590gx that routes the sense current of the selected channel to the diagnosis pin is. the channel is selected via spi register dcr.mux . the sense current also can be disabled by spi register dcr.mux . for details on timing of the current sense multiplexer, please refer to figure 18 . figure 18 timing of current sense multiplexer sensetiming.emf in v out i is t t t i l t on t on t sis(on) t sis(lc) off t off t dis (off) off muxtiming.emf cs i is t t 000 dcr.mux 001 111 111 t sis(en) t sis(mux) t dis(mux)
spi power controller spoc - bts 5590gx diagnosis data sheet 38 v1.1, 2006-09-20 4.4.3 switch bypass diagnosis to detect short circuit to v bb , there is a switch bypass monitor implemented. in case of short circuit between the output pin out and v bb in on-state, the current will flow through the power transistor as well as through the short circuit (bypass) with undefined ratio. as a result, the current sense signal will show lower values than expected by the load current. in off-state, the output voltage will stay close to v bb potential which means a small v ds . the switch bypass monitor compares the voltage v ds across the power transistor of that channel which is selected by the current sense multiplexer ( dcr.mux ) with threshold v ds(sb) . the result of comparison can be read in spi register hwcr.sbm . the switch bypass monitor is active in on- as well as in off-state.
spi power controller spoc - bts 5590gx diagnosis data sheet 39 v1.1, 2006-09-20 4.4.4 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. load current sense 4.4.1 current sense ratio k ilis channel 0, 1 (bulb): i l = 1.3 a i l = 2.6 a i l = 6.0 a 2400 2400 2500 3800 3500 3500 wdlr.ledn = 0 t j = -40 c i l = 1.3 a i l = 2.6 a i l = 6.0 a 2450 2450 2700 3600 3350 3300 t j = 150 c channel 0,1 (led): i l = 35 ma i l = 0.3 a i l = 0.7 a i l = 2.0 a 400 600 650 750 2200 1600 1400 1150 wdlr.ledn = 1 t j = -40 c i l = 35 ma i l = 0.3 a i l = 0.7 a i l = 2.0 a 500 650 700 800 2000 1500 1300 1130 t j = 150 c channel 2 (bulb): i l = 1.3 a i l = 2.6 a i l = 3.5 a 2400 2400 2500 3800 3500 3500 wdlr.ledn = 0 t j = -40 c i l = 1.3 a i l = 2.6 a i l = 3.5 a 2450 2450 2700 3600 3350 3300 t j = 150 c
spi power controller spoc - bts 5590gx diagnosis data sheet 40 v1.1, 2006-09-20 channel 2 (led): i l = 35 ma i l = 0.3 a i l = 0.7 a i l = 1.3 a 400 600 650 750 2200 1600 1400 1150 wdlr.ledn = 1 t j = -40 c i l = 35 ma i l = 0.3 a i l = 0.7 a i l = 1.3 a 500 650 700 800 2000 1500 1300 1130 t j = 150 c channel 3, 4: i l = 0.3 a i l = 0.6 a i l = 1.3 a i l = 2.0 a 550 650 700 700 1400 1200 1050 1050 t j = -40 c i l = 0.3 a i l = 0.6 a i l = 1.3 a i l = 2.0 a 600 680 720 720 1300 1100 1030 1030 t j = 150 c 4.4.2 current sense voltage limitation v is(lim) -8% v dd 8% v i is = 1 ma 4.4.3 current sense leakage, while diagnosis disabled i is(dis) 1 a i l = i l(nom) dcr.mux = 111 b 4.4.4 current sense settling time after channel activation t sis(on) 300 s v bb = 13.5 v i l = i l(nom) r is = 4.7 k ? wdlr.ledn = 0 115 wdlr.ledn = 1 4.4.5 current sense desettling time after channel deactivation t dis(off) 25 s v bb = 13.5 v 1) i l = i l(nom) r is = 4.7 k ? wdlr.ledn = 0 25 wdlr.ledn = 1 unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx diagnosis data sheet 41 v1.1, 2006-09-20 4.4.6 current sense settling time after change of load current channel 0, 1, 2 channel 3, 4 t sis(lc) 30 30 s v bb = 13.5 v 1) r is = 4.7 k ? wdlr.ledn = 0 i l = 1.3 a to 2.6 a i l = 0.6 a to 1.3 a 4.4.7 current sense settling time after current sense activation t sis(en) 25 s r is = 4.7 k ? dcr.mux : 111 b -> 000 b 4.4.8 current sense settling time after multiplexer channel change t sis(mux) 30 s r is = 4.7 k ? dcr.mux : 000 b -> 001 b 4.4.9 current sense deactivation time t dis(mux) 25 s r is = 4.7 k ? dcr.mux : 1) 001 b -> 111 b switch bypass monitor 4.4.10 switch bypass monitor threshold v ds(sb) 0.7 2.5 v 1) not subject to production test, specified by design. unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx diagnosis data sheet 42 v1.1, 2006-09-20 4.4.5 command description dcr diagnosis control registers 43210 0 0mux field bits type description mux 2:0 rw set current sense multiplexer configuration 000 current sense of channel 0 is routed to is pin 001 current sense of channel 1 is routed to is pin 010 current sense of channel 2 is routed to is pin 011 current sense of channel 3 is routed to is pin 100 current sense of channel 4 is routed to is pin 101 is pin is high impedance 110 is pin is high impedance 111 is pin is high impedance hwcr hardware configuration register w/r 43210 read lho wdl sbm pwm ctl write rst wdl 0 pwm ctl field bits type description sbm 2 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) 1) invalid in stand-by mode
spi power controller spoc - bts 5590gx diagnosis data sheet 43 v1.1, 2006-09-20 standard diagnosis cs76543210 ter 0 lhen wdl err4 err4 err2 err1 err0 field bits type description errn n = 4 to 0 nr error flag channel n 0 normal operation 1 failure mode occurred
spi power controller spoc - bts 5590gx limp home data sheet 44 v1.1, 2006-09-20 4.5 limp home the spoc - bts 5590gx provides a sophisticated watchdog function with trigger state machine to build a secure limp home signalling. the fail safe block is supplied via v bb and provides an output signal at pin lho in case of watchdog overrun independently of v dd . there is an enable pin lhen available which is usually connected to the ignition signal of the car. as soon as the limp home function is enabled, the watchdog is started and must be served. the timing can be adjusted in a wide range by choosing the appropriate capacitor. for calculation of the watchdog timing, please refer to section 4.5.1 . the watchdog is served via a trigger state machine, which starts at a defined state when limp home has been enabled. as a result, the state machine might also be reset to this startup state due to a voltage drop at pin lhen. a watchdog overrun causes the lho pin to turn from tri-state to a high signal. this signal can be utilized to switch on dedicated channels by connecting lho to the appropriate input pins and it is suitable to turn other hardware of the system into limp home mode as well. once the watchdog has been overrun, it can be reset by a low signal at pin lhen only. there is no software reset mechanism implemented for this function to make sure, a faulty software can not turn off the limp home mode. the status of the watchdog as well as the trigger state machine can be read via spi. as a result, the micro controller can perform a watchdog check via spi. please see following figure 19 for details. figure 19 block diagram: limp home limphome .emf gnd c wd lho lhen i lhd(c) vbb v l hd( r) power supply v lhd(o) i lhd(d) 0 1 trigger state machine or & wdtr wdc sub wdl or wdc += 1 lho lhen & lhd
spi power controller spoc - bts 5590gx limp home data sheet 45 v1.1, 2006-09-20 4.5.1 watchdog the watchdog function is built as analog trigger watchdog with external capacitor c wd as time base. a high signal at pin lhen enables the watchdog. a constant current loads the external capacitor, so the voltage rise is linear. when the watchdog is served, the capacitor is discharged to level v lhd(r) and the cycle starts again. please see following figure for details. figure 20 watchdog behavior the limp home out signal (lho) is generated, when the voltage at pin lhd exceeds threshold v lhd(o) . in this case, all spi registers are reset, but the read-only parameters ( lho , errn ) are still available. the spi interface including daisy chain capability is not affected by this reset signal. as a result it can be accessed normally. the maximum watchdog serve time which is the minimum watchdog overrun time t wd(o,min) is calculated by following formula: (1) the maximum watchdog overrun time t wd(o,max) is calculated by following formula: (2) there is an under voltage reset implemented in the watchdog block. in case of v bb lower than the operating voltage range of the watchdog (position 4.1.2 , v bb(wd) ), the lho driver is deactivated and the external capacitor c wd is discharged. as soon as the voltage rises above the under voltage threshold, the capacitor is charged again and the lho driver is activated. trigger t wat chdog. emf v lhd t t v lho lhen t wdc += 1 v l hd( o ) v l hd( r) wdtr == wdc t wd(o,min) c wd(min) v lhd(o,min) v lhd(r,max) ? () ? i lhd(c,max) ------------------------------------------------------------------------------------------------- = t wd(o,max) c wd(max) v lhd(o,max) v lhd(r,min) ? () ? i lhd(c,min) -------------------------------------------------------------------------------------------------- - =
spi power controller spoc - bts 5590gx limp home data sheet 46 v1.1, 2006-09-20 4.5.2 trigger state machine a trigger state machine is implemented to ensure secure limp home signalling. figure 21 trigger state machine there are two bits in the spi register block ( dcr.wdtr ) that have to be subsequently increased to serve the watchdog. the dwr.wdc parameter is increased by the device itself as soon as the capacitor is discharged below threshold v lhd(r) . the watchdog lock ( hwcr.wdl ) is set, when an incorrect dcr.wdtr value ( dcr.wdtr <> dcr.wdc ) has been written via spi. to serve the watchdog then, the lock bit has to be cleared and the correct dcr.wdtr value ( dcr.wdtr = dcr.wdc ) has to be written. the hwcr.wdl bit is also part of the standard diagnosis ( wdl ) and can be monitored at each spi access. the lock of the state machine trigger ensures that only correct handling will serve the watchdog. any incorrect dwr.wdtr value will lock the trigger for the watchdog, which will overrun after the specified timings. the trigger state machine is reset to the default values (see section 4.6.6 ) by the following events: ? pin lhen = low ? pin lho = 1 (limp home mode) ? the reset sources described in section 4.1.2 triggersm . emf v lhd v lhd(r) v lhd v l hd( r) v lh d v lh d(r ) v lh d v lhd(r) wd l 1 wd c 1 wd c 3 wd c 2 wd c 0 wdl= 0 wdtr < > wd c wd l = 0 w dt r <> w d c w dl =0 wd t r < > w dc w d l =0 w dt r < > w dc v lh e n = v lh en( l) v lhen = v lhen(h) lhen 0 v l h en = v lhen ( l ) lho 1 v l h d v l hd (o)
spi power controller spoc - bts 5590gx limp home data sheet 47 v1.1, 2006-09-20 4.5.3 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v lhen = 5 v typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. limp home 4.5.1 h-output voltage level of pin lho v lho(h) 59v v lhd = 5 v i lho = 1 ma 4.5.2 current limitation of pin lho i lho(lim) 2ma v lhd = 5 v watchdog 4.5.3 charge current for c wd i lhd(c) 15 22 30 a 4.5.4 discharge current for c wd -i lhd(d) 300 a 4.5.5 overrun threshold voltage at pin lhd v lhd(o) 4.0 4.4 4.8 v 4.5.6 recharge threshold voltage at pin lhd v lhd(r) 0.4 0.5 0.6 v input characteristics 4.5.7 l-input level at pin lhen v lhen(l) -0.3 1.0 v 4.5.8 h-input level at pin lhen v lhen(h) 2.6 5.5 v 4.5.9 l-input current through pin lhen i lhen(l) 385 a v lhen = 0.4 v 4.5.10 h-input current through pin lhen i lhen(h) 73085 a v lhen = 5 v
spi power controller spoc - bts 5590gx limp home data sheet 48 v1.1, 2006-09-20 4.5.4 command description wdlr watchdog and led mode configuration register w/r 43210 read wdc led2 led1 led0 write wdtr led2 led1 led0 field bits type description wd wdc wdtr 4:3 r w watchdog trigger state machine 11 watchdog trigger state machine counter (read only) 00 watchdog trigger register (write only) hwcr hardware configuration register w/r 43210 read lho wdl sbm pwm ctl write rst wdl 0 pwm ctl field bits type description lho 4 r limp home out 0 device is in normal operation mode 1 device is in limp home mode wdl 3 rw watchdog lock 0 watchdog can be served 1 watchdog state machine trigger is locked
spi power controller spoc - bts 5590gx limp home data sheet 49 v1.1, 2006-09-20 standard diagnosis cs76543210 ter 0 lhen wdl err4 err4 err2 err1 err0 field bits type description lhen 6 limp home enable 0 l-input signal at pin lhen 1 h-input signal at pin lhen wdl 5 watchdog lock 0 watchdog can be served 1 watchdog trigger state machine is locked
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 50 v1.1, 2006-09-20 4.6 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex synchronous serial slave interface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the rate given by sclk. the falling edge of cs indicates the beginning of an access. data is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred. the interface provides daisy chain capability. figure 22 serial peripheral interface 4.6.1 spi signal description cs - chip select: the system micro controller selects the spoc - bts 5590gx by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the requested information is transferred into the shift register. ? so changes from high impedance state to high or low state depending on the logic or combination between the transmission error flag ( ter ) and the signal level at pin si. as a result, even in daisy chain configuration, a high signal indicates a faulty transmission. this information stays available to the first rising edge of sclk. cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faulty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. sclk - serial clock: this input pin clocks the internal shift register. the serial input (si) transfers data into the shift register on the falling edge of sclk while the serial output lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 cs msb msb so si cs sclk time spi.emf
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 51 v1.1, 2006-09-20 (so) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shift-in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the input data consists of two parts, control bits followed by data bits. please refer to section 4.6.5 for further information. so serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appear at the so pin following the rising edge of sclk. please refer to section 4.6.5 for further information. 4.6.2 daisy chain capability the spi of spoc - bts 5590gx provides daisy chain capability. in this configuration several devices are activated by the same cs signal mcs . the si line of one device is connected with the so line of another device (see figure 23 ), in order to build a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the master device provides the master clock mclk which is connected to the sclk line of each device in the chain. figure 23 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out occures at the so pin. after eight sclk cycles, the data transfer for one device has been finished. in single chip configuration, the cs line must turn high to make the device accept the transferred data. in daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. when using three devices in daisy chain, three times eight bits have to be shifted through the devices. after that, the mcs line must turn high (see figure 24 ). si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _dasychain. emf
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 52 v1.1, 2006-09-20 figure 24 data transfer in daisy chain configuration 4.6.3 timing diagrams figure 25 timing diagram spi access mi mo mcs mclk s i devi ce 3 s i devi ce 2 si device 1 s o devi ce 3 s o devi ce 2 so device 1 time spi _dasychain2. emf cs sclk si t cs(lead) t cs( td ) t cs(lag) t scl k( h) t scl k( l ) t scl k( p) t si( su ) t si( h ) so t so( v) t so(en) t so( d is) 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd spi timing. emf
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 53 v1.1, 2006-09-20 4.6.4 electrical characteristics unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v dd = 3.8 v to 5.5 v typical values: v bb = 13.5 v, t j = 25 c, v dd = 4.3 v pos. parameter symbol limit values unit test conditions min. typ. max. input characteristics (cs , sclk, si) 4.6.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) -0.3 1.0 v v dd = 4.3 v 4.6.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 2.6 5.5 v v dd = 4.3 v 4.6.3 l-input pull-up current at cs pin i cs(l) 10 30 85 a v dd = 4.3 v v cs = 0 v 4.6.4 h-input pull-up current at cs pin i cs(h) 385 a v dd = 4.3 v v cs = 2.6 v 4.6.5 l-input pull-down current at pin sclk si i sclk(l) i si(l) 375 a v dd = 4.3 v v sclk = 0.4 v v si = 0.4 v 4.6.6 h-input pull-down current at pin sclk si i sclk(h) i si(h) 10 30 75 a v dd = 4.3 v v sclk = 4.3 v v si = 4.3 v output characteristics (so) 4.6.7 l level output voltage v so(l) 00.5v i so = -0.5 ma 4.6.8 h level output voltage v so(h) v dd - 0.5 v v dd v i so = 0.5 ma v dd = 4.3 v 4.6.9 output tristate leakage current i so(off) -10 10 a v cs = v dd timings 4.6.10 serial clock freqency f sclk 01mhz 4.6.11 serial clock period t sclk(p) 1 s 4.6.12 serial clock high time t sclk(h) 500 ns
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 54 v1.1, 2006-09-20 4.6.13 serial clock low time t sclk(l) 500 ns 4.6.14 enable lead time (falling cs to rising sclk) t cs(lead) 1 s 4.6.15 enable lag time (falling sclk to rising cs ) t cs(lag) 1 s 4.6.16 transfer delay time (rising cs to falling cs ) t cs(td) 2 s 4.6.17 data setup time (required time si to falling sclk) t si(su) 100 ns 4.6.18 data hold time (falling sclk to si) t si(h) 100 ns 4.6.19 output enable time (falling cs to so valid) t so(en) 1 s c l = 20 pf 1) 4.6.20 output disable time (rising cs to so tri- state) t so(dis) 1 s c l = 20 pf 1) 4.6.21 output data valid time with capacitive load t so(v) 500 ns c l = 20 pf 1) 1) not subject to production test, specified by design. unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v dd = 3.8 v to 5.5 v typical values: v bb = 13.5 v, t j = 25 c, v dd = 4.3 v pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 55 v1.1, 2006-09-20 4.6.5 spi protocol note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame the output at spi signal so will contain the requested information. a new command can be executed in the second frame. cs 1) 1) the so pin shows this information between cs hi -> lo and first sclk lo -> hi transition. 76543210 write register si 1 addr data read register si 0 addr xxxx0 read standard diagnosis si 0xxxxxx1 standard diagnosis so ter 0 lhen wdl err4 err3 err2 err1 err0 second frame of read command so ter 1 addr data field bits type description ter cs r transmission error 0 previous transmission was successful (modulo 8 clocks received) 1 previous transmission failed or first transmission after reset addr 6:5 rw address pointer to register for read and write command data 4:0 rw data data written to or read from register selected by address addr lhen 6 r limp home enable 0 l-input signal at pin lhen 1 h-input signal at pin lhen wdl 5 r watchdog lock 0 watchdog can be served 1 watchdog trigger state machine is locked
spi power controller spoc - bts 5590gx serial peripheral interface (spi) data sheet 56 v1.1, 2006-09-20 4.6.6 register overview errx x = 4 to 0 xr diagnosis of channel x 0 no failure 1 over temperature, over load or short circuit name w/r addr43210default 1) 1) the default values are set after reset. out w/r 00 b out4 out3 out2 out1 out0 00 h wdlr r 01 b wdc led2 led1 led0 18 h w01 b wdtr led2 led1 led0 00 h hwcr r 10 b lho wdl sbm pwm ctl 00 h w10 b rst wdl 2) 2) can be cleared only via spi. the bit is set by internal signals. 0pwmctl00 h dcr w/r 11 b 00 mux 07 h field bits type description
spi power controller spoc - bts 5590gx application description data sheet 57 v1.1, 2006-09-20 5 application description figure 26 application circuit example c vss spi vbb limp home lho lhd lhen gnd out3 out2 out1 out0 out4 gnd vbb ignition lho vcc v bat ad 20k ? 10k ? 10k ? 2k ? 2k ? 2k ? 2k ? 5v vdd vdd 100nf 500 ? lho 8k ? 8k ? 3. 3k ? 1k ? 1nf 470nf gpio gpio so sclk si cs is in1 in2 in3 in4 in0 circuit wd. emf spi 2k ? 10nf. . 100nf test schottky
spi power controller spoc - bts 5590gx package outlines spoc - bts 5590gx data sheet 58 v1.1, 2006-09-20 6 package outlines spoc - bts 5590gx figure 27 p-dso-36-20 (plastic dual small outline package) gps01089 2) does not include dambar protrusion of 0.05 max. per side 1) does not include plastic or metal protrusion of 0.15 max. per side 1 18 36 19 0.65 0.33 0.2 2.45 2.65 max. 0.1 -0.2 -0.1 0.23 +0.09 0.35 x 45? -0.2 1) 7.6 10.3 0.4 +0.8 8? max. +0.3 index marking 1) 12.8 -0.2 dimensions in mm you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
spi power controller spoc - bts 5590gx revision history data sheet 59 2006-09-20 7 revision history version date changes v1.1 06-09-20 page 18: register read value added
spi power controller spoc - bts 5590gx revision history data sheet 60 v1.1, 2006-09-20
spi power controller spoc - bts 5590gx data sheet 61 v1.1, 2006-09-20 edition 2006-09-20 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 2006. all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non- infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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